Prototype Verification System for 500-ps Wideband DC Pulse Particle Computing Based on the RFSOC 256-Channel Massive Array
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The system consists of 32 RFSoC 47DR circuit boards, each equipped with 8 ADCs and 8 DACs. The DAC sampling rate is 10 GHz, while the ADC sampling rate is 5 GHz. In total, there are 256 ADCs and 256 DACs.
Use a three-level clock to synchronize 256 ADCs and 256 DACs.
A parallel polyphase FIR filter is used to fine-tune the static delay between channels.
Clock networks are also used to synchronize logic structures, thereby reducing the number of cables and enhancing system reliability.
Dedicated hardware is designed specifically to process DC signals.
For the 256 ADCs and 256 DACs, the synchronization accuracy is ±10 ps. 
Image data is streamed from the server to the RFSoC board.
The 256 DACs on the RFSoC board transmit image data to the optical chip.
The 256 ADCs sample the data processed by the optical chip and send the data back to the server for further signal processing.
Channel output frequency: 100 kHz – 2 GHz Amplitude: Pmax 2VPP adjustable |
Channel Input Frequency: 100 kHz - 2 GHz |
DAC output of a 1000 ps wide signal |
DAC output of a 2000 ps wide signal |
DAC output of a 5000 ps wide signal |
Synchronize 4 DAC channels |
Synchronize 6 DAC channels from 6 different boards.
Video demonstration
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