RF24-VU13P HyperFusion Ultra‑Aggregation RF Processing Board
A high-performance data acquisition and processing platform. It comprises a high‑performance RF digital processing board built with three RFSOC28DR FPGAs and one VU13P FPGA. The system features 24 receive channels and 7 transmit channels, along with an extensive array of industrial control interfaces. It enables synchronous acquisition of 24‑channel data with an acquisition precision as fine as 2 ps. Once acquired, the 24‑channel data is transmitted at 1.2 Tbps via AURORA lanes to the downstream VU13P FPGA. The VU13P offers 12,288 DSP resources, 3,780K logic elements, and 455 Mbit of on‑chip memory. Leveraging the VU13P’s robust computational capabilities, it performs advanced signal processing tasks such as beamforming, pulse compression, and matched filtering. Processed results or raw data can be routed through 12 × 100G QSFP optical ports to memory‑reflection units and other downstream devices. Additionally, the system supports seven independent RF transmit channels. It is ideally suited for medium‑scale 7×24 MIMO systems and boasts excellent scalability, enabling multi‑board parallel operation and seamless integration with various large‑aperture arrays.
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Zynq UltraScale+ RFSOC Development Board
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- Commodity name: RF24-VU13P HyperFusion Ultra‑Aggregation RF Processing Board
A high-performance data acquisition and processing platform. It comprises a high‑performance RF digital processing board built with three RFSOC28DR FPGAs and one VU13P FPGA. The system features 24 receive channels and 7 transmit channels, along with an extensive array of industrial control interfaces. It enables synchronous acquisition of 24‑channel data with an acquisition precision as fine as 2 ps. Once acquired, the 24‑channel data is transmitted at 1.2 Tbps via AURORA lanes to the downstream VU13P FPGA. The VU13P offers 12,288 DSP resources, 3,780K logic elements, and 455 Mbit of on‑chip memory. Leveraging the VU13P’s robust computational capabilities, it performs advanced signal processing tasks such as beamforming, pulse compression, and matched filtering. Processed results or raw data can be routed through 12 × 100G QSFP optical ports to memory‑reflection units and other downstream devices. Additionally, the system supports seven independent RF transmit channels. It is ideally suited for medium‑scale 7×24 MIMO systems and boasts excellent scalability, enabling multi‑board parallel operation and seamless integration with various large‑aperture arrays.
A high-performance data acquisition and processing platform. It comprises a high‑performance RF digital processing board built with three RFSOC28DR FPGAs and one VU13P FPGA. The system features 24 receive channels and 7 transmit channels, along with an extensive array of industrial control interfaces. It enables synchronous acquisition of 24‑channel data with an acquisition precision as fine as 2 ps. Once acquired, the 24‑channel data is transmitted via a 1.2 Tbps AURORA link to the next‑level VU13P FPGA. The VU13P offers 12,288 DSP resources, 3,780K logic elements, and 455 Mbit of on‑chip memory. Leveraging the VU13P’s robust computational capabilities, it performs advanced signal processing tasks such as beamforming, pulse compression, and matched filtering. The processed results or raw data can be routed through 12 100G QSFP optical ports to downstream devices, including memory‑reflection units. Additionally, the system supports seven independent RF transmit channels. It is ideally suited for medium‑scale 7×24 MIMO systems and boasts excellent scalability, enabling multi‑board parallel operation and seamless integration with various large‑aperture arrays.
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Performance Metrics
FPGA chip
● 3x Zynq UltraScale+ XCZU28DR-2FFVG1517I RFSoC
● 1x Virtex UltraScale+ XCVU13P-2FLGA2577I
FPGAVU13P configuration interfaceStart the storage device
● 2XQSPI Flash (512 MB, 8-bit) with a pre‑configured firmware image
Memory Configuration
● 4xDDR4 (4GB, 64-bit, 2666 MT/s)
Expansion interface
● 1× USB–JTAG interface
● 10/100/1000 Ethernet RGMII (RJ45 interface)
Optical port
● 12X QSFP 28
External I/O Interface
● Z1: J30J-37PZKWP-J (default: 16 output channels and 16 input channels, with a typical supply voltage of 3.3 V LVTTL);
● Z1: J30J-37PZKWP-J (default: 16 output channels and 16 input channels, with a typical supply voltage of 3.3 V LVTTL);
● 1 dual-row 2×10 pin header (default: 8 input channels and 8 output channels, with a typical supply voltage of 3.3 V LVTTL);
● Z2: J30J-15ZKW-J (default configuration: 7 input channels and 7 output channels, with a typical supply voltage of 3.3 V LVTTL);
DAC interface
● Z1: X4 DAC (14-bit, 6.554 GSPS) ports
● Z2: X3 DAC (14-bit, 6.554 GSPS) ports
●Z3: ----
Three 28DR modules with identical interface configurations.
● ADC Interface: X8 ADC (12-bit, 4.096 GSPS) ports
Memory
● PS 2xDDR4 (2GB, 32-bit, 2400 MT/s)
● PL 4xDDR4 (4GB, 64-bit, 2666 MT/s)
PS-side interface
● 2x QSPI flash (256 MB, 8-bit) for storing configuration files
● 1x 10/100/1000 Ethernet RGMII (RJ45) network port
● 1x USB_JTAG
● 1x JTAG debugging interface
● 1x Micro SD Card
PL-side interface
● There are eight LVDS communication links between the three 28DRs, and between the three 28DRs and the 13P.
● There is an X16-lane GT communication link between each of the three 28DRs and the 13P.
● 1 UART interface
● 1x Button + 3x LED
Board power supply
● Dedicated power terminal (12V supply)
Size
● 330mm*377mm
Power consumption
● 42W (actual measured value, depending on the application)
Ambient temperature requirements
● Operating temperature: -40°C to 70°C
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