RFSOC-GPU Integrated High-Bandwidth RF Intelligent Processing Module
This product is an NVIDIA Orin GPU + RFSoC 47DR radar signal-processing platform, a high‑performance, heterogeneous, software‑hardware co‑processing architecture designed for modern radar systems. It seamlessly integrates the AI‑parallel computing capabilities of the NVIDIA Orin with the direct RF sampling and real‑time FPGA processing power of the AMD (Xilinx) RFSoC 47DR, specifically addressing the signal acquisition, real‑time processing, and AI inference requirements of wideband, multi‑channel, intelligent radars.
Model： IW-RFSOCZU47DR-GPU
Category:
Zynq UltraScale+ RFSOC Development Board
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- Product Details
- Product Specifications
- Product Features and Applications
- Shipping List
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- Commodity name: RFSOC-GPU Integrated High-Bandwidth RF Intelligent Processing Module
- 型号: IW-RFSOCZU47DR-GPU
This product is an NVIDIA Orin GPU + RFSoC 47DR radar signal-processing platform, a high‑performance, heterogeneous, software‑hardware co‑processing architecture designed for modern radar systems. It seamlessly integrates the AI‑parallel computing capabilities of the NVIDIA Orin with the direct RF sampling and real‑time FPGA processing power of the AMD (Xilinx) RFSoC 47DR, specifically addressing the signal acquisition, real‑time processing, and AI inference requirements of wideband, multi‑channel, intelligent radars.
IW_47dr1517_AGX of ZYNQ The chip is based on XILINX The company's Zynq TM UltraScale+ TM RFSoC Gen 3 Series XCZU47DR-2FFVG1517E , this board integrates advanced RF sampling ADC 、 DAC and FPGA Logic can directly process RF signals and is suitable for 5G Various application scenarios, including communications, radar, test and measurement, and satellite communications.
IW_47dr1517_AGX Used 4 piece Micron The company's DDR4 chip MT40A512M16LY-083 E IT:E ， and also P.S. Endpoint mounting 2 piece DDR4 Chip, composition 32 Bit data bus width, PL Endpoint mounting 2 piece DDR4 Chip, composition 32 Bit data bus width. The board also integrates two 2 G b of size QSPI FLASH Used to initialize storage configuration and system files. , providing fast non-volatile storage solutions 。IW_47dr1517_AGX board Carry two QSFP Fiber-optic interface, supporting multiple high-speed communication protocols, suitable for applications such as phased-array radar signal processing, electronic warfare, and… 5G MIMO and various other application scenarios 。
IW_47dr1517_AGX Board card Integrated 8 one 14 The sampling rate is 5GSPS of ADC and 8 one 14 The sampling rate is 9.85GSPS of DAC . In addition, it also integrates extra Jetson AGX Orin Embedded AI Computer. RFSOC and Jetson AGX Orin The two components collaborate through a division of labor, simultaneously meeting real-time constraints and delivering robust intelligent analysis capabilities. Meanwhile, the direct RF sampling architecture significantly reduces signal-chain latency, and their modular design further facilitates scalability.
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Performance Metrics
Technical Specifications
FPGA chip
Z YNQ UltraScale+ XCZU47DR-2FFVG1517E
RF Interface
1.X8 ADC ( 14-bit, 5G SPS) ports
2.X8 D A C ( 14-bit, 9.85G SPS) ports
Expand Memory
P.S. 2 xDDR4( 2GB,32 bit)
PL 2xDDR4( 2GB,32 bit)
Storage
- QSPI Flash 1 Gb *2 (RFSOCPS end )
- eMMC * 1(RFSOCPS end )
- SD card(RFSOCPS end )
- EEPROM*2( RFSOCPS End and AGX )
Board power supply
Power supply The input voltage is 12V
P.S. end Interface
- 1xSD Booth seating
PL End interface
- 2xQSFP Optical module
- 7xJ30J
Public interface
- 1xJ30J
- 1xUSB Interface
Jetson AGX Orin Interface
- 2xUSB3.0 Interface
- 1xDP Connector
- 1xM.2 Interface
Ambient temperature requirements
While working -40℃~ 70 °C
Reference Project
- Host Software Configuration ADC/DAC Related registers
- High speed ADC/DAC Loop Test Engineering
-Schematics ( .pdf Format)
- DDR4 Reference Design
- FPGA Pin arrangement -
Product Features
- RF direct‑sampling architecture eliminates analog‑chain bottlenecks.
- Compared with conventional superheterodyne receiver architectures, direct RF sampling technology eliminates analog processing stages such as mixing, filtering, and intermediate-frequency sampling, thereby significantly… Shorten signal-chain latency and reduce system power consumption and hardware complexity. 。
- FPGA Real-time preprocessing and AI Division of Labor and Collaboration in Reasoning
- Pulse compression, digital beamforming, constant false alarm rate detection ( CFAR ) and other algorithms in FPGA When implemented on the hardware, processing latency can be kept at the microsecond level or even sub-microsecond level. Jetson GPU It excels at handling compute‑intensive tasks rather than latency‑sensitive ones. This division of responsibilities enables the system to… It can both meet real-time constraints. , and also possesses strong Intelligent analysis capability 。
- PCIe Gen4 x8 High-speed interconnects ensure data throughput.
- RFSoC and Jetson between PCIe Gen4 x8 The link provides approximately 16 GB/s The theoretical bandwidth. From 8 Channel ADC original of IQ Data (by 5GSPS、14 Bit‑precision calculation, with a theoretical data rate of approximately 70 Gb/s ) After FPGA of the DDC After extraction and processing, the data rate can be reduced to a fraction of the original rate. 1/40 , satisfy PCIe The transmission capacity of the link.
- High-speed data recording and playback capability
- Platform support 8 Simultaneous continuous data acquisition and recording, in conjunction with… DAC The terminal’s playback function enables closed-loop testing of RF signals and scenario reproduction. . In actual system testing, transmission is conducted in a typical frequency band. EVM Superior to 1%， The phase consistency across channels meets the picosecond-level synchronization accuracy requirement. Applicable to systems such as phased-array radars that impose stringent requirements on channel consistency. 。
- Modular design, easy to expand
RFSoC Core board and Jetson The core board adopts a discrete, modular design, allowing users to tailor it to their computational power requirements. Replace with a different model. Jetson Module, or select different ones according to channel requirements. RFSoC Model number . The system supports multi‑board card cascaded synchronization and can, via an external clock distribution, synchronize multiple board cards’ ADC/DAC Channel synchronization is accurate to the picosecond level and has been extended to 16/32/64 A large-scale array system for the channel.
Product Applications
- Phased-array radar digital backend
RFSoC Complete 8 Synchronous acquisition and digital beamforming across channels (or multiple channels in a multi‑board cascade), Jetson Run object detection, trajectory tracking, and classification recognition. Compared with traditional… “ADC” board + Server ” Compared with the previous scheme, system integration has been enhanced, and the data transmission path has been shortened.
- Electronic Warfare:
RFSoC Perform real-time scanning across the entire frequency band and extract the time–frequency features of the signal. Jetson Employ deep learning models to identify threat types—such as frequency-hopping signals and radar waveforms—and generate jamming or deception strategies. FPGA Handle low latency, GPU High-throughput reasoning, with the two working in tandem, meets the dynamic response requirements of adversarial environments.
- 5G Massive MIMO Prototype validation ：
Single board provided 8 Channel transceiver capability; multi-board cascading can be scaled up to 32 or 64 Channel, suitable for baseband processing in large-scale antenna arrays. Jetson It can deploy beam management, user scheduling, and channel prediction, among other functions. AI Model, utilizing TensorRT Accelerate real-time decision-making 。
- Spectrum Monitoring and Signal Intelligence:
Wideband ( 1 MHz~6 GHz ) Continuous capture capability, in conjunction with Jetson A signal classification and emitter fingerprint identification model running on the edge can close the loop from detection to identification entirely at the edge, without relying on cloud servers.
- Satellite communication terminal:
Integrated design meets requirements for size, weight, and power consumption ( SWaP ) Limited terminal scenarios. RFSoC Complete above / Downconversion and baseband processing in the protocol stack, Jetson Operates link-adaptive algorithms and traffic management, supporting 100GbE and PCIe Expansion interface 。
- RF direct‑sampling architecture eliminates analog‑chain bottlenecks.
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