40G TOE IP
A professional, high-performance network processor IP core that fully offloads TCP, UDP, ARP, ICMP, IGMP, IP, MAC, and other protocols. It is suitable for data transmission in scenarios such as network storage, audio‑video processing, and edge computing in data centers, delivering high‑bandwidth, low‑latency, high‑quality network connectivity. XOE can completely free up CPU resources previously consumed by TCP/IP, with the IPCore achieving a single‑core throughput of 40 Gbps, meeting the demands of multi‑connection applications on high‑speed Ethernet and supporting up to 256 concurrent TCP/UDP connections.
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- Commodity name: 40G TOE IP
A professional, high-performance network processor IP core that fully offloads TCP, UDP, ARP, ICMP, IGMP, IP, MAC, and other protocols. It is suitable for data transmission in scenarios such as network storage, audio‑video processing, and edge computing in data centers, delivering high‑bandwidth, low‑latency, high‑quality network connectivity. XOE can completely free up CPU resources previously consumed by TCP/IP, with the IPCore achieving a single‑core throughput of 40 Gbps, meeting the demands of multi‑connection applications on high‑speed Ethernet and supporting up to 256 concurrent TCP/UDP connections.
A professional, high-performance network processor IP core that fully offloads TCP, UDP, ARP, ICMP, IGMP, IP, MAC, and other protocols. It is suitable for data transmission in scenarios such as network storage, audio‑video processing, and edge computing in data centers, delivering high bandwidth, low latency, and high‑quality network data transfer. XOE can completely free up CPU resources previously consumed by TCP/IP, with a single‑core throughput of up to 40 Gbps, meeting the demands of multi‑connection applications on high‑speed Ethernet and supporting up to 256 concurrent TCP/UDP connections.
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IP Implementation Framework:
X2001-TUALL provides an AXI‑ST interface on the network side for connecting an external 40G MAC; this MAC IP core is either Xilinx’s official MAC or a third‑party IP core. On the user side, it offers standard AXI4‑MM or AXI‑ST interfaces, allowing compatibility with different bus architectures based on the user’s system design. In the example shown, an ARM AMBA bus is used, and both the data and configuration interfaces employ AXI plus DMA for data transfer.Resource occupancy status
Actual test results
Unidirectional transmission test 2LAN error injection test Bidirectional communication speed test
RX rate: 4500 MB/s, approximately 36 Gbps/s RX rate: 4500 MB/s, approximately 36 Gbps/s RX rate: 3500 MB/s, approximately 28 Gbps/s
Correctness: correct accumulates continuously, while error remains at 0. Correctness: injection errors cause link exceptions; all other cases are normal. TX rate: 3600 MB/s, approximately 29 Gbps.
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